This application is related to U.S. patent application Ser. No. 10/060,724 (Attorney Docket No. NOVE100028000), filed the same day and assigned to the same assignee as the present application, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method for depositing titanium (Ti) liner layers and titanium nitride (TiN) barrier layers for applications in semiconductor processing having improved via and contact resistance.
2. Description of Related Art
In the manufacture of semiconductor devices, metal conductive layers are patterned for the purpose of making interconnections between different points on the device. After formation of this patterned metal conductive layer an electrically insulative material is deposited over the metal conductive layer. Vias may then be etched in the insulative layer in positions where contacts are desired between conductive regions. A robust diffusion barrier, or liner, may then be deposited into the via between the underlying metal and a metal layer deposited therein, such as by chemical vapor deposition of tungsten (W), for the formation of a stud. The robust diffusion barrier both prevents attack of the underlying metal and acts as an adhesion layer for stud.
In modern integrated circuit (xe2x80x9cICxe2x80x9d) technology, a metallization comprising a Ti layer, a TiN layer and a top conductive layer is often provided on a surface of a semiconductor body. The Ti layer serves to obtain good adhesion and low contact resistance between the metallization and the semiconductor body. Typically, the TiN layer serves as a barrier between a top conductive layer of Al and the underlying Ti layer, thereby preventing chemical reactions there-between. That is, the Ti layer reduces any oxide left on the underlying Al layer after a sputter preclean step, thus allowing for low contact resistance. Alternatively, the TiN layer may serve as a barrier between the Ti layer and a top conductive layer of W deposited using WF6, thereby preventing chemical reactions between Ti and F which is formed during such a CVD process. Additionally, the TiN layer is needed to improve the adhesion of the CVD W for a following CMP removal step. An anti-reflective coating (xe2x80x9cARCxe2x80x9d) of TiN can also be deposited on the surface of the W or Al. Thus, a typical stack arrangement on an IC semiconductor substrate may include a Ti contact layer on the semiconductor surface, a TiN barrier layer, a W or Al interconnect layer, and a TiN ARC layer for the purpose of reducing optical reflection.
These films are generally deposited by physical vapor deposition (PVD), also known as sputtering. Various physical vapor deposition (xe2x80x9cPVDxe2x80x9d) sputtering techniques known in the art for depositing TiN/Ti stacks may be categorized as either nitrided mode (xe2x80x9cNMxe2x80x9d), i.e., poisoned mode, or non-nitrided mode (xe2x80x9cNNMxe2x80x9d), i.e., metallic mode. In the NM (nitrided mode), typically a titanium target is placed in a sputter chamber, and the TiN layers are deposited by sputtering titanium with a sputter gas, such as argon (xe2x80x9cArxe2x80x9d), in the presence of nitrogen. In a NM technique, the titanium target is inundated with nitrogen atoms, becoming xe2x80x9cnitridedxe2x80x9d, such that a coating of TiN forms on the surface of the titanium target. This decreases the overall deposition rate of the desired layer of TiN onto the IC substrate because the nitrogen in the titanium target interferes with the sputtering of titanium. A disadvantage is that the titanium target used to deposit TiN cannot then be used to deposit Ti. As a result, various separate deposition chamber techniques have been introduced in the art for depositing each of the Ti and TiN layers.
It is also known in the art to deposit the Ti/TiN stacks in the non-nitrided mode (xe2x80x9cNNMxe2x80x9d), i.e., metallic mode. Deposition of TiN in the NNM keeps the N2 away from the target, hence, the target being non-nitrided or the target being in a metallic mode. In the NNM, the depositions of the Ti and TiN layers may be performed in the same deposition chamber, allowing for a higher throughput for the PVD system and allowing redundancy to be built into the system. It has been found that TiN deposited in the NNM mode tends to be a poor barrier by itself, often requiring having to anneal the NNM TiN deposited layer, such as by Rapid Thermal Nitridation or Rapid Thermal Anneal, to improve the TiN barrier properties. In so doing, the annealing step improves the barrier properties by causing growth at the grain boundary of the TiN, thereby reducing the diffusion of WF6 gas used for the CVD deposition of a W layer thereover, and hence improving the barrier properties. The nitridation or anneal step also influences the nucleation (initial growth steps) of the CVD W and plays an influential role in the final film properties of the CVD W film that is grown on the TiN barrier film. However, having to anneal the NNM TiN deposited layer requires additional processing steps and, as such, increases both time and processing expenses.
It is also known in the art to use a shutter that allows deposition of Ti and TiN in the same deposition chamber. A Ti layer is first deposited using a Ti target. Then, a TiN layer is deposited on the Ti layer using the same Ti target in a NM. During TiN deposition in the NM, the Ti target becomes nitrided, i.e., poisoned. Before depositing the Ti layer on the next wafer, the shutter is inserted between the target and the wafer, and the target is sputtered in the absence of nitrogen gas to sputter away the nitrided components to return the target to its clean, metallic state and ready for the sputtering of pure Ti. To reduce the inefficiency of using a shutter or separate chambers for Ti and TiN deposition, modifications in the sputtering sequence have been suggested in the prior art, such as, the deposition of an extra Ti layer to sputter away the nitrogen in the nitrided titanium target, returning it to a pure Ti state, thereby reducing the number of chambers being used. However, the use of an extra titanium layer has the disadvantage that if a CVD W layer is deposited on the extra Ti layer using WF6, any free Ti reacts with F to form a layer of TiFs, to which W has a bad adhesion. Accordingly, the use of a shutter in the deposition processes of Ti and TiN layers also requires additional processing steps, increases processing time, and increases processing costs.
As the aspect ratio (xe2x80x9cARxe2x80x9d) of the via increases, i.e., the ratio of the height of the aperture to its width, it has been found that conventional sputtering techniques do not provide acceptable deposition results. As the AR increases, far less material is being deposited at the bottom of the vias than at the top surfaces of the vias, since the sidewalls xe2x80x9cshadowxe2x80x9d the lower exposed surface. The deposited material at the upper surfaces increasingly accentuates the shadowing effect, thereby prematurely closing the upper section of the via and preventing effective fill of the lower section. For example, with a conventional sputter method, bottom coverage is only about 5% in a via having an AR of 5:1. In order to improve the deposition of Ti and TiN into vias having increased AR, collimation sputtering techniques have been developed in the art.
Collimation techniques having a collimating filter, as known in the art, between the target and the substrate impart greater directionality to the atoms reaching the substrate surface. The use of a collimator allows deposition of Ti and TiN in vias with aspect ratios up to about 2 or 3. However, collimation techniques are inefficient as much of the target material is wasted and builds up on the cell walls of the filter which can lead to an undesired increase in the number of particulates in the system, making it necessary to replace or clean the collimator frequently. Also, since most of the sputtered material does not pass through the collimator and is wasted, the deposition rate is slow and the rate of consumption of the target is high. To overcome such problems, prior art has been aimed at increasing the sputter power in the NM to obtain a practical growth rate, however, when increasing the sputter power it is also necessary to increase the flow rate of nitrogen. This causes the growth rate of the TiN film to be reduced to less than one-third under the same sputter power as compared with the case in which Ti film is formed by such sputtering process.
A collimator can also be used in a NNM process in which N2 gas enters the deposition chamber towards the wafer substrate and is prevented from passing through the collimator towards the target by the flow of Ti atoms. In such a process, it is necessary to exactly balance and control the sputter power and the flow rates of inert Ar and N2 gases, however, such control is difficult and the Ti targets often become nitrided. In either case, a collimator used in either a NM or a NNM mode eventually becomes covered with deposits of Ti and TiN material which tend to flake off the collimator, resulting in contamination of the underlying IC substrate.
Accordingly, it has been recognized that conventional PVD sputtering techniques are inefficient and, in some instances, incapable of providing required directionality to thin films when fabricating VLSI and ULSI circuits. In accordance with standard PVD sputtering devices and techniques, the plasma created lacks a sufficient amount of ionized target material atoms, referred to as plasma intensity. The more intense the plasma, the greater the ability to steer and focus the plasma and thus impart an adequate amount of directionality to the ions in the plasma. The application of RF power to a band of material of the sputtered species, that is the same as the target, was introduced to improve the ability of a sputter source to fill grooves and vias. In so doing, the RF power couples into the neutral plasma and increases the ionization of the neutral atoms. However, the disadvantages with this method is that the band also gets sputtered, and becomes a consumable. Additionally, the sputtering of the band can increase the amount of particles created.
The use of magnetic fields in magnetron sputtering devices has also been introduced in the art to overcome the limitations of conventional PVD sputtering. The magnetic field serves to attract an electron-rich portion of the plasma in the vicinity of the target, whereby the electrons trapped about the target allow for an increase in the collisions between neutral atoms ejected from the surface of the target and the rapidly moving electrons. By increasing the quantity of collisions, the likelihood increases that a neutral ejected target atom will be struck by a sufficiently energetic particle within the plasma, thus causing the ejected target atom to lose one or more electrons and result in an ionized atom. By increasing the quantity of ionized target atoms within the plasma, the plasma density increases and so does the probability that further ionization of ejected target atoms will occur. However, conventional magnetron and rf-iPVD sputtering techniques are limited in their efficiency as the vast majority of metal atoms ejected from the target remain neutral, i.e., upwards of 98% or greater of the target material atoms remain un-ionized as they travel through the sputter chamber to the substrate. As with other PVD techniques, Ti-atoms are ejected from the surface of the sputter target at a random angle and the mean-free path of travel between the target cathode and the substrate for these neutral metal atoms is reduced by random collisions with other target atoms or inert gas ions. When the predominantly neutral atoms in these plasmas do come in contact with the substrate, they characteristically do so over a wide range of angles, generally conforming to a cosine distribution. In particular, when atoms are deposited on substrate surfaces at angles less than normal, it poses significant difficulty in uniformly filling trenches and interconnect vias. Accordingly, the overall efficiency of such systems are very low as most of the sputtered material remains unionized.
A technique that improves directionality of the depositing species and therefore improves the step coverage is ionized PVD (IPVD). IPVD techniques typically allow for thinner Ti/TiN film thicknesses due to improved bottom and sidewall coverage, which in turn, allows for less over-polish time and therefore less dishing and scratching during the CMP process of a W layer thereover the Ti/TiN films. Several techniques have been employed to achieve IPVD such as Radio Frequency biased IPVD (RFIPVD), Ion Metal Plasma (IMP), and Hollow Cathode Magnetron (HCM) can be named. However, many of the IPVD sources suffer from the fact that they cannot produce a sufficiently high density plasma that can adequately ionize the depositing metal species. The RFIPVD and IMP IPVD sources produce medium plasma densities in the order 1-5xc3x971011 particles/cm3. This tends to limit the application of medium density plasma IPVD sources (RFIPVD and IMP) for certain applications including that of Ti and TiN liner and barrier layers in semiconductor processing. Additionally, as the successful management of the thermal budget is critical to a successful implementation of I-PVD, I-PVD for Ti and TiN has not been successfully introduced into semiconductor production due to the temperature control needed for the wafer during ionized deposition. The thermal budget is a measure of the time that the substrate spends at a higher temperature, as well as the continuous period of time that the substrate is at an elevated temperature. Including the instant cooling steps allows the substrate temperature to decrease, and thus interrupts activity related to thermal budget, such as, grain structure orientation and growth, diffusion of impurities, and the like. The cooling step of the instant invention also prevents the continued growth of grains for each of the Ti layer and the TiN layer. Further, in accordance with the invention, cooling the substrate prior to depositing the Ti layer and the TiN layer also minimizes the out-gassing of impurities from the surface of the substrate which leads to a clean interface between the aluminum line and the Ti layer, as well as a clean interface between the Ti layer and the TiN layer.
As the critical dimension of semiconductor devices continue to become smaller, the patterned contact or via holes get narrower and deeper, i.e. the aspect ratio of the contacts or vias increase. As such, Ti/TiN liner and barrier depositions for low contact resistance tungsten interconnects continues to be a major challenge for current and future aspect ratios of interconnect vias. Standard PVD techniques are proven to be inadequate for depositing films in narrow, high aspect ratio structures with necessary and sufficient step coverage as well as the necessary and sufficient via and contact resistance. Accordingly, a need continues to exist in the art for improved methods of depositing Ti liner layers and TiN barrier layers for high aspect ratio of contacts or vias having sufficient via and contact resistance.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of depositing robust Ti liner layers and TiN barrier layers having improved via and contact resistance.
Another object of the present invention is to provide a method of depositing Ti liner layers and TiN barrier layers having reduced grain boundaries so that barrier liner performance is not compromised.
It is another object of the present invention to provide a method of depositing conformal Ti/TiN barrier layers within a high aspect ratio opening on a semiconductor wafer such that a metal layer does not diffuse past the barrier layer.
A further object of the invention is to provide a method of depositing Ti/TiN liner and barrier layers within a single deposition chamber, without the use of a collimator or shutter.
It is yet another object of the present invention to provide a method of depositing Ti/TiN liner and barrier layers having decreased processing steps, time and at reduced costs.
Still another object of the present invention is to provide a method of depositing Ti/TiN liner and barrier layers which imparts increased directionality to the atoms reaching the substrate surface.
Another object of the invention is to provide a method of depositing Ti/TiN liner and barrier layers having improved step coverage, grain size, grain orientation and roughness.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects, which will be apparent to those skilled in art, are achieved in the present invention which is directed to, in a first aspect, a method of forming a Ti layer and a TiN layer on an integrated circuit substrate in a single PVD deposition chamber without using either a collimator or a shutter. The method includes the steps of providing a hollow cathode target containing titanium whereby the hollow cathode target has a cavity region and providing a substrate attached to an electrostatic chuck within the hollow cathode target. A layer containing Ti is formed on the substrate by sputtering Ti from the target and then a layer containing TiN is formed on the substrate by sputtering Ti from the target while simultaneously flowing a nitrogen-containing gas into the deposition chamber.
In accordance with the first aspect of the invention, the temperature of the substrate is controlled prior to deposition of at least one of the layer containing Ti on said substrate or the layer containing TiN on said substrate. In so doing, the temperature of the substrate may be controlled by applying a temperature controlled electrostatic chuck, or alternatively, by cooling the substrate by time delay.
In a second aspect, the invention relates to a method of forming a Ti layer and a TiN layer on an integrated circuit substrate in a single PVD deposition chamber without using either a collimator or a shutter. The method includes the steps of providing a hollow cathode target containing titanium whereby the hollow cathode target has a cavity region and providing a substrate attached to an electrostatic chuck within the hollow cathode target. The temperature of the substrate is controlled prior to depositing the layer containing Ti on the substrate, and then Ti is sputtered from a target to form such layer containing Ti. The temperature of the substrate is also controlled prior to depositing the layer containing TiN on the substrate. The layer containing TiN is then formed on the substrate by sputtering Ti from the target while simultaneously flowing a nitrogen-containing gas into the deposition chamber.
In accordance with the invention, the temperature of the substrate may be controlled prior to depositing both the Ti layer and the TiN layer by applying a temperature controlled electrostatic chuck, or alternatively, by cooling the substrate by time delay. Wherein the substrate is cooled by time delay, the substrate is allowed to cool for a range from about 20 seconds to about 120 seconds for both the Ti and the TiN layers.
The invention is characterized in that the single deposition chamber does not contain either a collimator or a shutter. The semiconductor wafer may have at least one via formed thereon. The instant method of forming the Ti and TiN layers on an integrated circuit substrate in a single PVD deposition chamber without using either a collimator or a shutter may further include creating a magnetic field having a magnetic null region located between the cavity region and the substrate, heating the substrate to a temperature in a range from about 25xc2x0 C. to 350xc2x0 C., and applying a negative volt in a range from about xe2x88x92400 to about xe2x88x92500 volts to the hollow cathode target. The method may still further include applying an amount of power in a range from about 20 to about 36 kilowatts to the hollow cathode target and applying a current not exceeding 1.0 amps to an electromagnetic coil.
Preferably, the hollow cathode target and the substrate are separated by a source-to-substrate spacing from about 86 mm to about 106 mm. Still further, the source-to-substrate spacing may be the same during the depositions of the layer containing Ti on the substrate and the layer containing TiN on the substrate. Alternatively, the source-to-substrate spacing may differ during the depositions of the layer containing Ti on the substrate and the layer containing TiN on the substrate. In the invention, the deposited Ti layer may have a thickness in a range from about 10 nm to about 70 nm, while the deposited TiN layer has a thickness in a range from about 10 nm to about 100 nm.
In still a further aspect of the invention, the invention relates to a method of forming a Ti layer and a TiN layer on an integrated circuit substrate in a single PVD deposition chamber without using either a collimator or a shutter. The method includes the steps of providing a hollow cathode target containing titanium whereby the hollow cathode target has a cavity region and providing a substrate attached to an electrostatic chuck within the hollow cathode target. The temperature of the substrate is controlled prior to depositing the layer containing Ti on the substrate by applying a temperature controlled electrostatic chuck to said substrate in addition to cooling said substrate by time delay. The Ti layer is then sputtered from a target to form such layer containing Ti. The temperature of the substrate is also controlled prior to depositing the layer containing TiN on the substrate by applying a temperature controlled electrostatic chuck to said substrate in addition to cooling said substrate by time delay. The layer containing TiN is then formed on the substrate by sputtering Ti from the target while simultaneously flowing a nitrogen-containing gas into the deposition chamber.